The invention relates to a method of manufacturing a semiconductor device with a MOS transistor, by which method a gate dielectric and a gate electrode are formed on a surface of a silicon substrate, whereupon the surface next to the gate electrode is exposed, a layer of semiconductor material is formed in the silicon substrate on an edge of the surface adjoining the gate electrode with the gate electrode and the layer of semiconductor material acting as a mask, ions are implanted, and a heat treatment is carried out so as to form a source zone and a drain zone through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material.
The source and drain zones of the MOS transistor are formed during the heat treatment. One portion of each of these zones is formed through activation of implanted ions and another portion through diffusion of atoms of a dopant from the layer of semiconductor material. These portions are simultaneously formed during the heat treatment, the former portion lying next to the layer of semiconductor material and the latter portion merging into the former and lying below the layer of semiconductor material. The quantity of dopant provided by implantation and the quantity of dopant provided by diffusion can be adjusted independently of one another. This is done as follows in practice: the former portions of the source and drain zones are comparatively strongly doped, and the second portions comparatively weakly. The portion lying below the gate electrode, which is not doped here, forms the channel zone of the MOS transistor. The comparatively weakly doped portion is accordingly present between the comparatively strongly doped portion and the channel zone. Such a structure is sometimes referred to as LDD (lightly doped drain) structure.
The formation of the comparatively shallow and weakly doped portion of the source and drain zones through diffusion from the layer of semiconductor material also renders it possible to form a very shallow zone. Zones having a depth of less than 10 nm can thus be realized, which is practically impossible by means of ion implantation followed by a heat treatment.
U.S. Pat. No. 5,391,508 discloses a method of the kind mentioned in the opening paragraph whereby a layer of semiconductor material consisting of silicon is provided on the edge of the surface which adjoins the gate electrode. To achieve this, a side wall insulation is first formed on the gate electrode after the surface next to the gate electrode has been exposed, i.e. a layer of insulating material is deposited, whereupon the surface next to the gate electrode is again exposed by means of an anisotropic etching treatment, such that the side wall insulation remains. A silicon layer is subsequently deposited and then subjected to an anisotropic etching treatment which is stopped when a comparatively thin silicon layer is still present on the gate electrode and on the surface. A comparatively thick silicon layer is still present on the side wall of the gate electrode then. Subsequently, the assembly is subjected to a thermal oxidation treatment whereby the deposited silicon is oxidized so far that it is completely converted into silicon oxide on the gate electrode and on the surface. A layer of silicon covered by silicon oxide then remains on the side wall of the gate electrode and on the edge of the surface adjoining the gate electrode. The silicon layer covered with silicon oxide is subsequently doped by means of an oblique implantation.
Not only does the known method comprise many process steps which are difficult to control, but it has the particular disadvantage that the silicon layer covered with silicon oxide remains present in the MOS transistor. This doped layer connected to the source or drain zone is insulated from the gate electrode by a thin silicon oxide layer. As a result of this, parasitic capacitances arise of which especially the gate-drain capacitance is disadvantageous to the operation of the MOS transistor.
Neither is it possible to remove the silicon layer covered with silicon oxide at the area of the MOS transistor. After etching away of the silicon oxide layer formed by thermal oxidation, in fact, both the silicon layer on the edge adjoining the gate electrode and the silicon of the substrate next to this edge would be exposed. This means that, when the silicon layer is etched away from the edge adjoining the gate electrode, the same quantity of silicon would be removed from the substrate situated next to the edge.
In practice, the gate electrode forms a conductor track having a beginning and an end. The silicon layer covered with silicon oxide is formed also on this beginning and this end. This silicon layer forms an electrical connection between the silicon layer covered with silicon oxide and formed on the side walls of the gate electrode. At one side of the gate this silicon layer is connected to the source, at the other side to the drain of the MOS transistor. Thus a short-circuit between source and drain is formed. This short-circuit can only be eliminated by means of additional process steps. The beginning and end have to be provided, for example, on a layer of a material other than silicon, and portions of the gate electrode lying on silicon have to be protected with a photoresist mask during the removal of the silicon covered with silicon oxide.